Thursday 18 June 2026
RV64GC Profile v2.4 Ratified
The application profile is frozen and signed off — base integer, multiply, atomics, float, double and compressed, verified against the golden model. →
Exclusive
Thursday 18 June 2026
OpenR5 2.4 — Verified Cores, End to End
The 2.4 release lands the RV64GC application profile with formal sign-off across the full pipeline — fetch to retire — plus golden-model co-simulation gating every commit. Four reference cores, one ratified ISA, zero royalties.
Vector 1.0 is upstream in both GCC and LLVM, and the R5-App core now boots mainline Linux on commodity FPGAs in under ninety seconds.
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The News
Tuesday 9 June 2026
Vector 1.0 Lands in LLVM
Auto-vectorization for RVV 1.0 is now upstream in both major compilers, with scalable vectors and the full arithmetic set wired through. →
Friday 29 May 2026
R5-App Boots Linux 6.9 on FPGA
A full mainline boot — MMU, supervisor mode and trap handling — on a commodity board in under ninety seconds, end to end. →
Monday 18 May 2026
Hypervisor Extension Enters Review
The 'H' extension RFC opens for public review — two-stage translation, virtual supervisor mode and a reference KVM port. →
Extensions
MODULAR ISA · RV32 / RV64
MMUL/DIV
AATOMIC
FFLOAT
DDOUBLE
CCOMPRESS
VVECTOR